//################################################################################
// MIT License
// Copyright (c) 2024 ZhangYihua
//
// Change Logs:
// Date           Author       Notes
// 2020-07-13     ZhangYihua   first version
//
// Description  : global head file must be added fistly while compiling or synthesising
//################################################################################

// define U_DLY <space> for synthesis to avoid warning, and define U_DLY #0.1 for simulation
`ifndef U_DLY
    `define U_DLY
`endif

// define vendor or process library
`define FPGA

//`define FPGA_EFX
//`define FPGA_ALTERA
`define FPGA_XILINX

//`define ASIC

// define the following macro for better area and timing
`define ARRAY_ADDR_OUT_OF_RANGE_RD_X

// define the following macro for rounding before truncation
//`define TRUNCATION_WITH_ROUNDING

// define the following macro for undefined parameter check
//`define PARAMETER_NULL_CHECK  
